Singapore chip startup Symatics unveils new AI chip architecture MPU, aiming to reduce inference latency

Singapore-based semiconductor startup Symatics unveiled its Morphic Processing Unit (MPU) architecture at the 2026 Business and Philanthropy Forum, claiming the design cuts inference latency for interactive AI workloads by optimizing how data is organized and processed. The architecture uses row-column parallel processing and compiler-planned execution to reduce data movement between memory and compute units, targeting inference rather than training. Symatics plans to license the open architecture and collaborate with Singapore research institutions and industry partners. The MPU remains in R&D with technical validation ongoing, and the company has not disclosed funding, prototype silicon, or tape-out progress. The announcement matters as a bid to challenge established AI chip designs on latency rather than raw throughput; next milestones to watch are a prototype chip, tape-out timeline, and licensing partners.